The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the wafer surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5min. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. Meanwhile, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min at 300°C, but show significant degradation after the initial annealing for 5min at 400°C. The C-t analysis is a useful method to electrically characterize the influence of Cu contamination from the Cu TSV on device reliability in fabricated LSI wafers.