Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory

Kanuku Ri, S. Tanikawa, M. Murugesan, H. Naganuma, Jichoru Be, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The Young's modulus (E) of Si substrate begins to noticeably decrease below 50-μm thickness. The Young's modulus in 30-μm thick Si substrate decreased by approximately 30% compared to the modulus of 50-μm thickness. In 30-μm thick Si substrate, the lattice structure of Si substrate is highly distorted. Large distortion of the lattice structure induces the Young's modulus reduction, consequently weakens the mechanical strength. A DRAM chip of 200-μm thickness was bonded to a Si interposer and thinned down to 50/40/30/20-μm thickness, respectively. The retention characteristics of DRAM cell are degraded depending on the decreased chip thickness, especially dramatically degraded below 50-μm thickness. The retention time of DRAM cell in 20-μm thick chip is shortened by approximately 40% compared to the 50-μm thick chip, regardless of the well structure (triple-well, twin-well). The distortion of the lattice structure in the thin chip effects a minority carrier generation lifetime, consequently shortening the retention time of DRAM cell.

Original languageEnglish
Title of host publication2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States
Duration: 2013 Oct 22013 Oct 4

Publication series

Name2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
CountryUnited States
CitySan Francisco, CA
Period13/10/213/10/4

Keywords

  • 3D DRAM
  • Si Young's modulus
  • mechanical strength
  • retention time

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

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  • Cite this

    Ri, K., Tanikawa, S., Murugesan, M., Naganuma, H., Be, J., Fukushima, T., Tanaka, T., & Koyanagi, M. (2013). Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. In 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 [6702336] (2013 IEEE International 3D Systems Integration Conference, 3DIC 2013). https://doi.org/10.1109/3DIC.2013.6702336