Image processing VLSI architecture based on data compression

Masanori Hariyama, Hisashi Yoshida, Michitaka Kameyama, Yasuhiro Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

To design low-power and high-speed image processors, the reduction of the number of interconnection units plays an important role. This paper presents a data-compression-based VLSI architecture that reduces the number of interconnection units between processing elements and memory modules without performance degradation. For example of a stereo matching VLSI, the number of interconnection units is reduced to 75%. The signal transition, which directly affects the dynamic power for data transfer, is also reduced to 50%.

Original languageEnglish
Title of host publication2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Pages430-433
Number of pages4
DOIs
Publication statusPublished - 2008
Event2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS - Knoxville, TN, United States
Duration: 2008 Aug 102008 Aug 13

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Other

Other2008 IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS
Country/TerritoryUnited States
CityKnoxville, TN
Period08/8/1008/8/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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