IC implementation of a switched-current chaotic neuron

Rubén Herrera, Ken Suyama, Yoshihiko Horio, Kazuyuki Aihara

Research output: Contribution to journalArticlepeer-review

17 Citations (Scopus)


A switched-current integrated circuit, which realizes the chaotic neuron model, is presented. The circuit mainly consists of CMOS inverters that are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using a 1.2 μm HP CMOS process. A single neuron cell occupies only 0.0076mm2, which represents an area smaller than the one occupied by a standard bonding pad. The circuit operation was tested at a clock frequency of 2 MHz.

Original languageEnglish
Pages (from-to)1776-1781
Number of pages6
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number9
Publication statusPublished - 1999 Jan 1
Externally publishedYes


  • Chaotic neural network
  • Switched-current circuits

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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