IC implementation of a current-mode chaotic neuron

Ruben Herrera, Ken Suyama, Yoshihiko Horio

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

An IC implementation of a new current-mode chaotic neuron is presented. The circuit mainly consists of CMOS inverters, which are used as transconductance amplifiers and nonlinear elements. The chip was fabricated using 1.2 μm HP CMOS process. One neuron occupies only 0.0076 mm2, which is smaller than a standard bonding pad. The circuit was tested at a clock frequency of 2 MHz.

Original languageEnglish
Pages (from-to)546-549
Number of pages4
JournalUnknown Journal
Volume3
Publication statusPublished - 1998
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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