Highly scalable 3-D vertical FG NAND cell arrays using the Sidewall Control Pillar (SCP)

Moon Sik Seo, Jong Moo Choi, Sung Kye Park, Tetsuo Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

In this paper, we propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the sidewall control pillar (SCP). This novel cell consists of cylindrical FG and SCP with a line type control gate (CG) structure. For simplifying the process flow, we propose to fabricate the cylindrical SCP structure by using the self-aligned process with the deposition of the poly silicon pillar. In order to compensate the increase of the channel capacitance, we decrease the floating gate width by about 15nm, which is comparable thickness to recent charge trap layer, and adopt the high-k material for inter poly dielectric (IPD). As a result, we successfully demonstrate the program with 18V at Vth=4V and erase with 17V at Vth=-3V, that are comparable performances in comparison with the conventional FG NAND cells by using the device simulator. Moreover, using the proposed SCP NAND cell, the interference margin with cell space length has been successfully extended and the same vertical scaling as the charge trap (CT) type 3D NAND cell also can be realized for 2Xnm technology. Above all, the proposed cell has good potential for Terabit 3-D vertical NAND cell with high manufacturability.

Original languageEnglish
Title of host publication2012 4th IEEE International Memory Workshop, IMW 2012
DOIs
Publication statusPublished - 2012 Jul 27
Event2012 4th IEEE International Memory Workshop, IMW 2012 - Milano, Italy
Duration: 2012 May 202012 May 23

Publication series

Name2012 4th IEEE International Memory Workshop, IMW 2012

Other

Other2012 4th IEEE International Memory Workshop, IMW 2012
Country/TerritoryItaly
CityMilano
Period12/5/2012/5/23

Keywords

  • 3-D Vertical Stacked Cell
  • Cylindrical FG
  • Floating Gate
  • GAA
  • NAND flash memory
  • Sidewall Control Gate
  • Sidewall Control Pillar

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Highly scalable 3-D vertical FG NAND cell arrays using the Sidewall Control Pillar (SCP)'. Together they form a unique fingerprint.

Cite this