TY - GEN
T1 - Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link
AU - Mochizuki, Akira
AU - Shirahama, Hirokatsu
AU - Onizawa, Naoya
AU - Hanyu, Takahiro
PY - 2015/2/5
Y1 - 2015/2/5
N2 - A single-ended current-mode interface circuit with a single-rail wire is proposed for a high-speed and highly reliable inter-chip communication link in an asynchronous network-on-chip system. The impedance of the single-rail wire is matched to the impedance of the receiver by inserting the MOS transistors, and the current signal level on the link is enlarged in the proposed interface circuit. As a result, crosstalk noise superposed on a single-rail wire can be reduced. It is demonstrated that the noise influences are eliminated under 130nm and 65nm CMOS technologies.
AB - A single-ended current-mode interface circuit with a single-rail wire is proposed for a high-speed and highly reliable inter-chip communication link in an asynchronous network-on-chip system. The impedance of the single-rail wire is matched to the impedance of the receiver by inserting the MOS transistors, and the current signal level on the link is enlarged in the proposed interface circuit. As a result, crosstalk noise superposed on a single-rail wire can be reduced. It is demonstrated that the noise influences are eliminated under 130nm and 65nm CMOS technologies.
UR - http://www.scopus.com/inward/record.url?scp=84937830478&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2014.7032873
DO - 10.1109/APCCAS.2014.7032873
M3 - Conference contribution
AN - SCOPUS:84937830478
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 683
EP - 686
BT - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2014 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2014
Y2 - 17 November 2014 through 20 November 2014
ER -