TY - GEN
T1 - Highly reliable multiple-valued circuit based on dual-rail differential logic
AU - Mochizuki, Akira
AU - Hanyu, Takahiro
PY - 2006/11/21
Y1 - 2006/11/21
N2 - A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise reduction. Since a dual-rail complementary duplication is performed by using two differential-pair circuits (DPCs), noise effect is distributed to only one DPC, if common-mode, noise is applied to dual-rail input lines. The dual-rail complementary duplicated DPCs makes noise effect reduced, because one of the DPC makes error operation and the other makes no-error operation, so that the output noise level which is summed up of two DPCs becomes half. By using the Schmitt-trigger circuit, the half-level noise effect from two DPCs is almost eliminated. As a typical design example of arithmetic modules, it is discussed to implement a crosstalk-noise-free radix-2 signed-digit full adder in a 0.18μm CMOS technology at the supply voltage of 1.8V.
AB - A new multiple-valued circuit based on dual-rail differential logic is proposed for crosstalk noise reduction. Since a dual-rail complementary duplication is performed by using two differential-pair circuits (DPCs), noise effect is distributed to only one DPC, if common-mode, noise is applied to dual-rail input lines. The dual-rail complementary duplicated DPCs makes noise effect reduced, because one of the DPC makes error operation and the other makes no-error operation, so that the output noise level which is summed up of two DPCs becomes half. By using the Schmitt-trigger circuit, the half-level noise effect from two DPCs is almost eliminated. As a typical design example of arithmetic modules, it is discussed to implement a crosstalk-noise-free radix-2 signed-digit full adder in a 0.18μm CMOS technology at the supply voltage of 1.8V.
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U2 - 10.1109/ISMVL.2006.24
DO - 10.1109/ISMVL.2006.24
M3 - Conference contribution
AN - SCOPUS:33751068745
SN - 0769525326
SN - 9780769525327
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
BT - 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
T2 - 36th International Symposium on Multiple-Valued Logic, 2006. ISMVL 2006
Y2 - 17 May 2006 through 20 May 2006
ER -