Highly parallel collision detection VLSI processor for intelligent robots

Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

A collision detection VLSI processor is proposed for achieving ultrahigh performance processing with an ideal parallel processing scheme. Coordinate transformation and inference check in 3-dimensional task space are fully utilized in the processing algorithm, so that direct collision detection can be executed with VLSI-oriented regular data flow. The structure of the processing element (PE) is very simple because a coordinate rotation digital computer (CORDIC) arithmetic unit for coordinate transformation and a few memories are included as the main components. Evaluation shows that the chip can be developed with a reasonable size of 5.1 × 12.7 mm2 and the typical collision detection time is about 384 μsec using 100 PEs. The performance is about ten thousand times faster than that of the conventional approach using general-purpose processors.

Original languageEnglish
Pages29-30
Number of pages2
Publication statusPublished - 1991 Dec 1
Event1991 Symposium on VLSI Circuits - Oiso, Jpn
Duration: 1991 May 301991 Jun 1

Other

Other1991 Symposium on VLSI Circuits
CityOiso, Jpn
Period91/5/3091/6/1

ASJC Scopus subject areas

  • Engineering(all)

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