Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system

H. Hashimoto, T. Fukushima, K. W. Lee, M. Koyanagi, T. Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.

Original languageEnglish
Title of host publication2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs
Publication statusPublished - 2013 Dec 1
Event2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States
Duration: 2013 Oct 22013 Oct 4

Publication series

Name2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
CountryUnited States
CitySan Francisco, CA
Period13/10/213/10/4

Keywords

  • TSV self-repair
  • TSV test
  • Through Silicon Via (TSV)

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Computer Science Applications

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