TY - GEN
T1 - Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system
AU - Hashimoto, H.
AU - Fukushima, T.
AU - Lee, K. W.
AU - Koyanagi, M.
AU - Tanaka, T.
PY - 2013
Y1 - 2013
N2 - Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.
AB - Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.
KW - TSV self-repair
KW - TSV test
KW - Through Silicon Via (TSV)
UR - http://www.scopus.com/inward/record.url?scp=84893918056&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84893918056&partnerID=8YFLogxK
U2 - 10.1109/3DIC.2013.6702338
DO - 10.1109/3DIC.2013.6702338
M3 - Conference contribution
AN - SCOPUS:84893918056
SN - 9781467364843
T3 - 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
BT - 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
T2 - 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
Y2 - 2 October 2013 through 4 October 2013
ER -