Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system

H. Hashimoto; T. Fukushima; K. W. Lee; M. Koyanagi; T. Tanaka

doi:10.1109/3DIC.2013.6702338

Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system

H. Hashimoto, T. Fukushima, K. W. Lee, M. Koyanagi, T. Tanaka

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.

Original language	English
Title of host publication	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
DOIs	https://doi.org/10.1109/3DIC.2013.6702338
Publication status	Published - 2013 Dec 1
Event	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013 - San Francisco, CA, United States Duration: 2013 Oct 2 → 2013 Oct 4

Publication series

Name	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013

Other

Other	2013 IEEE International 3D Systems Integration Conference, 3DIC 2013
Country	United States
City	San Francisco, CA
Period	13/10/2 → 13/10/4

Keywords

TSV self-repair
TSV test
Through Silicon Via (TSV)

ASJC Scopus subject areas

Computer Graphics and Computer-Aided Design
Computer Science Applications

Access to Document

10.1109/3DIC.2013.6702338

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Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. / Hashimoto, H.; Fukushima, T.; Lee, K. W.; Koyanagi, M.; Tanaka, T.

2013 IEEE International 3D Systems Integration Conference, 3DIC 2013. 2013. 6702338 (2013 IEEE International 3D Systems Integration Conference, 3DIC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hashimoto, H, Fukushima, T, Lee, KW, Koyanagi, M & Tanaka, T 2013, Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. in 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013., 6702338, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, 2013 IEEE International 3D Systems Integration Conference, 3DIC 2013, San Francisco, CA, United States, 13/10/2. https://doi.org/10.1109/3DIC.2013.6702338

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