Over the scaling limit, 3D LSI using Through Silicon Vias (TSVs) brings in a huge number of additional logic gates. 3D LSI technology allows LSIs to adopt redundant or spare modules in order to raise its availability, dependability or resiliency. For such 3D LSI, the one of the most important matter is to increase the connectivity of vertical connections between stacked tiers. To achieve a resilient 3-D stacked multicore processor system, it is indispensable to develop TSV self-test and self-repair circuit. Especially, it is important to reduce redundant TSVs with large-pitch because of their area cost while increasing its repairability. The processor chip for the resilient 3-D stacked multicore processor has been designed and fabricated with highly area-efficient TSV repair technology.