Highly efficient GF(28) inversion circuit based on redundant GF arithmetic and its application to AES design

Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Yasuyuki Nogami, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

This paper proposes a compact and efficient GF(28) inversion circuit design based on a combination of non-redundant and redundant Galois Field (GF) arithmetic. The proposed design utilizes redundant GF representations, called Polynomial Ring Representation (PRR) and Redundantly Represented Basis (RRB), to implement GF(28) inversion using a tower field GF((24)2). In addition to the redundant representations, we introduce a specific normal basis that makes it possible to map the former components for the 16th and 17th powers of input onto logic gates in an efficient manner. The latter components for GF(24) inversion and GF(24) multiplication are then implemented by PRR and RRB, respectively. The flexibility of the redundant representations provides efficient mappings from/to the GF(28). This paper also evaluates the efficacy of the proposed circuit by means of gate counts and logic synthesis with a 65 nm CMOS standard cell library and comparisons with conventional circuits, including those with tower fields GF(((22)2)2). Consequently, we show that the proposed circuit achieves approximately 40% higher efficiency in terms of area-time product than the conventional best GF(((22)2)2) circuit excluding isomorphic mappings. We also demonstrate that the proposed circuit achieves the best efficiency (i. e., area-time product) for an AES encryption S-Box circuit including isomorphic mappings.

Original languageEnglish
Title of host publicationCryptographic Hardware and Embedded Systems - 17th International Workshop, CHES 2015, Proceedings
EditorsTim Güneysu, Helena Handschuh
PublisherSpringer-Verlag
Pages63-80
Number of pages18
ISBN (Print)9783662483237
DOIs
Publication statusPublished - 2015 Jan 1
EventInternational Workshop on Cryptographic Hardware and Embedded Systems, CHES 2015 - Saint-Malo, France
Duration: 2015 Sep 132015 Sep 16

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume9293
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

OtherInternational Workshop on Cryptographic Hardware and Embedded Systems, CHES 2015
CountryFrance
CitySaint-Malo
Period15/9/1315/9/16

Keywords

  • AES
  • Compact hardware implementation
  • GF(2) inversion
  • S-Box

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Ueno, R., Homma, N., Sugawara, Y., Nogami, Y., & Aoki, T. (2015). Highly efficient GF(28) inversion circuit based on redundant GF arithmetic and its application to AES design. In T. Güneysu, & H. Handschuh (Eds.), Cryptographic Hardware and Embedded Systems - 17th International Workshop, CHES 2015, Proceedings (pp. 63-80). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 9293). Springer-Verlag. https://doi.org/10.1007/978-3-662-48324-4_4