Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology

K. W. Lee, H. Hashimoto, M. Onishi, S. Konno, Y. Sato, C. Nagai, J. C. Bea, M. Murugesan, T. Fukushima, T. Tanaka, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.

Original languageEnglish
Title of host publication2014 IEEE International Electron Devices Meeting, IEDM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages28.6.1-28.6.4
EditionFebruary
ISBN (Electronic)9781479980017
DOIs
Publication statusPublished - 2015 Feb 20
Event2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
Duration: 2014 Dec 152014 Dec 17

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
NumberFebruary
Volume2015-February
ISSN (Print)0163-1918

Other

Other2014 60th IEEE International Electron Devices Meeting, IEDM 2014
CountryUnited States
CitySan Francisco
Period14/12/1514/12/17

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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