The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
|Number of pages||2|
|Journal||Digest of Technical Papers - Symposium on VLSI Technology|
|Publication status||Published - 1998 Jan 1|
|Event||Proceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA|
Duration: 1998 Jun 9 → 1998 Jun 11
ASJC Scopus subject areas
- Electrical and Electronic Engineering