Abstract
The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
| Original language | English |
|---|---|
| Pages (from-to) | 124-125 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - Symposium on VLSI Technology |
| Publication status | Published - 1998 Jan 1 |
| Externally published | Yes |
| Event | Proceedings of the 1998 Symposium on VLSI Technology - Honolulu, HI, USA Duration: 1998 Jun 9 → 1998 Jun 11 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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Tanabe, N., Kobayashi, S., Miwa, T., Amanuma, K., Mori, H., Inoue, N., Takeuchi, T., Saitoh, S., Hayashi, Y., Yamada, J., Koike, H., Hada, H., & Kunio, T. (1998). High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics. Digest of Technical Papers - Symposium on VLSI Technology, 124-125.