TY - JOUR
T1 - High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics
AU - Tanabe, N.
AU - Kobayashi, S.
AU - Miwa, T.
AU - Amanuma, K.
AU - Mori, H.
AU - Inoue, N.
AU - Takeuchi, T.
AU - Saitoh, S.
AU - Hayashi, Y.
AU - Yamada, J.
AU - Koike, H.
AU - Hada, H.
AU - Kunio, T.
PY - 1998/1/1
Y1 - 1998/1/1
N2 - The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
AB - The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.
UR - http://www.scopus.com/inward/record.url?scp=0031632787&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0031632787&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0031632787
SP - 124
EP - 125
JO - Digest of Technical Papers - Symposium on VLSI Technology
JF - Digest of Technical Papers - Symposium on VLSI Technology
SN - 0743-1562
T2 - Proceedings of the 1998 Symposium on VLSI Technology
Y2 - 9 June 1998 through 11 June 1998
ER -