TY - GEN
T1 - High throughput/gate FN-based hardware architectures for AES-OTR
AU - Ueno, Rei
AU - Homma, Naofumi
AU - Iida, Tomonori
AU - Minematsu, Kazuhiko
PY - 2019/1/1
Y1 - 2019/1/1
N2 - This paper presents high throughput/gates Feistel network (FN)-based AES-OTR hardware architectures. AES-OTR is an authenticated encryption (AE) scheme as a block cipher mode of operation using AES. While AES-OTR is one of the most theoretically efficient AEs using AES and has superior features, its practical efficiency in hardware is unclear due to no known reports of its hardware implementation. In this paper, we present efficient AES-OTR hardware architectures. In contrast to conventional AE architectures, our architecture forms the 2-round FN of OTR, which makes it easy to integrate the peripheral into hardware for OTR operations. The proposed architectures had 2.4 and 13.5 times higher throughput/gates than the de facto standard AE (i.e., AES-GCM) core on FPGA and ASIC, respectively, through logic syntheses.
AB - This paper presents high throughput/gates Feistel network (FN)-based AES-OTR hardware architectures. AES-OTR is an authenticated encryption (AE) scheme as a block cipher mode of operation using AES. While AES-OTR is one of the most theoretically efficient AEs using AES and has superior features, its practical efficiency in hardware is unclear due to no known reports of its hardware implementation. In this paper, we present efficient AES-OTR hardware architectures. In contrast to conventional AE architectures, our architecture forms the 2-round FN of OTR, which makes it easy to integrate the peripheral into hardware for OTR operations. The proposed architectures had 2.4 and 13.5 times higher throughput/gates than the de facto standard AE (i.e., AES-GCM) core on FPGA and ASIC, respectively, through logic syntheses.
KW - AES-OTR
KW - Authenticated encryption
KW - Cryptographic hardware architecture
UR - http://www.scopus.com/inward/record.url?scp=85066808034&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85066808034&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2019.8702231
DO - 10.1109/ISCAS.2019.8702231
M3 - Conference contribution
AN - SCOPUS:85066808034
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
Y2 - 26 May 2019 through 29 May 2019
ER -