High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean Luc Danger

Research output: Contribution to journalArticle

Abstract

This article proposes highly efficient Advanced Encryption Standard (AES) hardware architectures that support encryption and both encryption and decryption. New operation-reordering and register-retiming techniques presented in this article allow us to unify the inversion circuits in SubBytes and InvSubBytes without any delay overhead. In addition, a new optimization technique for minimizing linear mappings, named multiplicative-offset, further enhances the hardware efficiency. We also present a shared key scheduling datapath that can work on-the-fly in the proposed architecture. To the best of our knowledge, the proposed architecture has the shortest critical path delay and is the most efficient in terms of throughput per area among conventional AES encryption/decryption and encryption architectures with tower-field S-boxes. The proposed round-based architecture can perform AES encryption where block-wise parallelism is unavailable (e.g., cipher block chaining (CBC) mode); thus, our techniques can be globally applied to any type of architecture including pipelined ones. We evaluated the performance of the proposed and some conventional datapaths by logic synthesis with the NanGate 45-nm open-cell library. As a result, we can confirm that our proposed architectures achieve approximately 51-64 percent higher efficiency (i.e., higher bps/GE) and lower power/energy consumption than the other conventional counterparts.

Original languageEnglish
Article number8922779
Pages (from-to)534-548
Number of pages15
JournalIEEE Transactions on Computers
Volume69
Issue number4
DOIs
Publication statusPublished - 2020 Apr 1

Keywords

  • AES
  • hardware architectures
  • round-based encryption architecture
  • unified encryption/decryption architecture

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

Fingerprint Dive into the research topics of 'High Throughput/Gate AES Hardware Architectures Based on Datapath Compression'. Together they form a unique fingerprint.

  • Cite this

    Ueno, R., Homma, N., Morioka, S., Miura, N., Matsuda, K., Nagata, M., Bhasin, S., Mathieu, Y., Graba, T., & Danger, J. L. (2020). High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Transactions on Computers, 69(4), 534-548. [8922779]. https://doi.org/10.1109/TC.2019.2957355