High-throughput partially parallel inter-chip link architecture for asynchronous multi-chip NoCs

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

Research output: Contribution to journalArticlepeer-review

Abstract

This paper introduces a partially parallel inter-chip link architecture for asynchronous multi-chip Network-on-Chips (NoCs). The multi-chip NoCs that operate as a large NoC have been recently proposed for very large systems, such as automotive applications. Inter-chip links are key elements to realize high-performance multi-chip NoCs using a limited number of I/Os. The proposed asynchronous link based on level-encoded dual-rail (LEDR) encoding transmits several bits in parallel that are received by detecting the phase information of the LEDR signals at each serial link. It employs a burst-mode data transmission that eliminates a per-bit handshake for a high-speed operation, but the elimination may cause datatransmission errors due to cross-talk and power-supply noises. For triggering data retransmission, errors are detected from the embedded phase information; error-detection codes are not used. The throughput is theoretically modelled and is optimized by considering the bit-error rate (BER) of the link. Using delay parameters estimated for a 0.13 μm CMOS technology, the throughput of 8.82 Gbps is achieved by using 10 I/Os, which is 90.5% higher than that of a link using 9 I/Os without an error-detection method operating under negligible low BER (< 10-20).

Original languageEnglish
Pages (from-to)1546-1556
Number of pages11
JournalIEICE Transactions on Information and Systems
VolumeE97-D
Issue number6
DOIs
Publication statusPublished - 2014 Jun

Keywords

  • Asynchronous circuits
  • Burst-mode data transmission
  • Data retransmission
  • Error detection
  • Level-encoded dual-rail (ledr) encoding
  • Network-on-chip (noc)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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