High throughput parallel arithmetic circuits for fast fourier transform

Ryosuke Nakamoto, Sakae Sakurabaf, Alexandra Martins, Takeshi Onomi, Shigeo Satof, Koji Nakajima

Research output: Contribution to journalArticlepeer-review


We have designed and implemented a 4-bit Carry Look-ahead Adder (CLA) and 4-bit parallel multipliers to be used for the Fast Fourier Transform (FFT) system with the estimated clock frequency of 20 GHz. Through some high frequency functional tests, we have confirmed that the operation of the CLA has been successful. Through some low speed tests, we have also confirmed that the operation of multiplication has been successful. In addition, we have designed a 4-bit multiplier with a Booth encoder and with a 2-point-4-bit butterfly circuit.

Original languageEnglish
Pages (from-to)280-287
Number of pages8
JournalIEICE Transactions on Electronics
Issue number3
Publication statusPublished - 2011 Mar


  • Adder
  • Multiplier
  • SFQ
  • Super-conductive circuits, FFT

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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