High-speed timing verification scheme using delay tables for a large-scaled multiple-valued current-mode circuit

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current-mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.

Original languageEnglish
Title of host publicationProceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages70-75
Number of pages6
DOIs
Publication statusPublished - 2008 Sep 3
Event38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States
Duration: 2008 May 222008 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Country/TerritoryUnited States
CityDallas, TX
Period08/5/2208/5/24

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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