High-speed pipelined hardware architecture for galois counter mode

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

In the authenticated encryption mode GCM (Galois Counter Mode), the CTR (counter) mode for data encryption that has no feedback path can easily be pipelined to boost the operating frequency of a hardware implementation. However, the hash function for the authentication tag generation performs multiply-add operations sequentially by chaining the result in the previous cycle, and this becomes the critical path in the high-speed GCM hardware. Therefore, we propose a high-speed pipelined hardware architecture for GCM in conjunction with a pipelined multiply-adder on a Galois field GF(2 128). This architecture was implemented with a 4-stage pipelined multiply-adder and a 56-stage pipelined AES (Advanced Encryption Standard) circuit by using a 0.13-um CMOS standard cell library. This implementation showed very high throughput of 54.94 Gbps with 272 Kgates for the key lengths of 128, 192, and 256 bits. The high hardware efficiency (throughput/gate) of 201.75 Kbps/gate is also an improvement over prior art.

Original languageEnglish
Title of host publicationInformation Security - 10th International Conference, ISC 2007, Proceedings
PublisherSpringer Verlag
Pages118-129
Number of pages12
ISBN (Print)9783540754954
DOIs
Publication statusPublished - 2007 Jan 1
Event10th Information Security Conference, ISC 2007 - Valparaiso, Chile
Duration: 2007 Oct 92007 Oct 12

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume4779 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other10th Information Security Conference, ISC 2007
CountryChile
CityValparaiso
Period07/10/907/10/12

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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