TY - GEN

T1 - HIGH-SPEED COMPACT MULTIPLIER BASED ON MULTIPLE-VALUED BI-DIRECTIONAL CURRENT-MODE CIRCUITS.

AU - Kawahito, Shoji

AU - Kameyama, Michitaka

AU - Higuchi, Tatsuo

AU - Yamada, Haruyasu

PY - 1987/1/1

Y1 - 1987/1/1

N2 - A high-speed compact multiplier using 2- mu m CMOS technology based on the radix-4 signed-digit (SD) number system is designed and implemented. The multiplier chip, composed of multiple-valued bidirectional current-mode circuits, can perform 32- multiplied by 32-bit twos-complement multiplication with only three stage SD full adders, based on a binary-tree addition scheme. The chip contains about 24,000 transistors at a total size of 7. 16 multiplied by 4. 92 mm**2. The multiply time is less than 59 ns. The performance comparable to that of the fastest binary multiplier is achieved in half of that multiplier's size.

AB - A high-speed compact multiplier using 2- mu m CMOS technology based on the radix-4 signed-digit (SD) number system is designed and implemented. The multiplier chip, composed of multiple-valued bidirectional current-mode circuits, can perform 32- multiplied by 32-bit twos-complement multiplication with only three stage SD full adders, based on a binary-tree addition scheme. The chip contains about 24,000 transistors at a total size of 7. 16 multiplied by 4. 92 mm**2. The multiply time is less than 59 ns. The performance comparable to that of the fastest binary multiplier is achieved in half of that multiplier's size.

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M3 - Conference contribution

AN - SCOPUS:0023166891

SN - 0818607750

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 172

EP - 180

BT - Proceedings of The International Symposium on Multiple-Valued Logic

PB - IEEE

ER -