HIGH-SPEED COMPACT MULTIPLIER BASED ON MULTIPLE-VALUED BI-DIRECTIONAL CURRENT-MODE CIRCUITS.

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

A high-speed compact multiplier using 2- mu m CMOS technology based on the radix-4 signed-digit (SD) number system is designed and implemented. The multiplier chip, composed of multiple-valued bidirectional current-mode circuits, can perform 32- multiplied by 32-bit twos-complement multiplication with only three stage SD full adders, based on a binary-tree addition scheme. The chip contains about 24,000 transistors at a total size of 7. 16 multiplied by 4. 92 mm**2. The multiply time is less than 59 ns. The performance comparable to that of the fastest binary multiplier is achieved in half of that multiplier's size.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherIEEE
Pages172-180
Number of pages9
ISBN (Print)0818607750
Publication statusPublished - 1987 Jan 1

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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