A high-speed compact multiplier using 2- mu m CMOS technology based on the radix-4 signed-digit (SD) number system is designed and implemented. The multiplier chip, composed of multiple-valued bidirectional current-mode circuits, can perform 32- multiplied by 32-bit twos-complement multiplication with only three stage SD full adders, based on a binary-tree addition scheme. The chip contains about 24,000 transistors at a total size of 7. 16 multiplied by 4. 92 mm**2. The multiply time is less than 59 ns. The performance comparable to that of the fastest binary multiplier is achieved in half of that multiplier's size.