High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits

Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalArticle

31 Citations (Scopus)

Abstract

This paper presents a very-Iarge-scale-integration (VLSI)-oriented high-speed multiplier design method based on carry-propagation-free addition trees and a circuit technique, so-called multiple-valued current-mode (MVCM) circuits. The carry-propagation-free addition method uses a redundant digit set such as {0,1, 2, 3} and {0, 1, 2. 3, 4}. The number representations using such redundant digit sets are called redundant positive-digit number representations. The carry-propagation-free addition is written by three steps, and the adder can be designed directly and efficiently from the algorithm using MVCM circuits. The designed multiplier internally using the MVCM parallel adder with the digit set {0, 1, 2, 3} in radix 2 has attractive features on speed, regularity of the structure, and reduced complexities of active elements and interconnections. A prototype CMOS integrated circuit of the MVCM parallel adder has been implemented, and its stable operation has been confirmed. Other possible schemes of multipliers with redundant digit sets using MVCM technology are discussed.

Original languageEnglish
Pages (from-to)34-42
Number of pages9
JournalIEEE Transactions on Computers
Volume43
Issue number1
DOIs
Publication statusPublished - 1994 Jan

Keywords

  • Area-efficient design
  • VLSI
  • carry-propagation-free ad-
  • dition
  • high-speed multiplier
  • multiple-valued current-mode circuits
  • redundant number representations
  • tree structure

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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