High-speed and low-power n+-p+ double-gate SOI CMOS

Kunihiro Suzuki, Tetsu Tanaka, Yoshiharu Tosaka, Hiroshi Horie, Toshihiro Sugii

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

We propose and fabricate n+-p+ double-gate SOI MOSFETs for which threshold voltage is controlled by interaction between the two gates. Devices have excellent short channel immunity, despite a low channel doping concentration of 1015 cm-3, and enable us to design a threshold voltage below 0.3 V while maintaining an almost ideal subthreshold swing. We demonstrated 27 ps CMOS inverter delay with a gate length of 0.19 μm, which is, to our knowledge, the lowest delay for this gate length despite rather a thick 9 nm gate oxide. This high performance is a result of the low threshold voltage and negligible drain capacitance. We also showed theoretically that we can design a 0.1 μm gate length device with an ideal subthreshold swing, and that we can expect less than 10 ps inverter delay at a supply voltage of 1 V.

Original languageEnglish
Pages (from-to)360-367
Number of pages8
JournalIEICE Transactions on Electronics
VolumeE78-C
Issue number4
Publication statusPublished - 1995 Apr 1
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., & Sugii, T. (1995). High-speed and low-power n+-p+ double-gate SOI CMOS. IEICE Transactions on Electronics, E78-C(4), 360-367.