A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.
|Number of pages||3|
|Publication status||Published - 1986 Jan 1|
ASJC Scopus subject areas
- Electrical and Electronic Engineering