HIGH-SPEED AND HIGH-CODING-GAIN VITERBI DECODER WITH LOW POWER CONSUMPTION EMPLOYING SST (SCARCE STATE TRANSITION) SCHEME.

S. Kubota, K. Ohtani, S. Kato

Research output: Contribution to journalArticlepeer-review

17 Citations (Scopus)

Abstract

A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS masterslice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good P//e performance (4. 2 db net coding gain at P//e equals 1 multiplied by 10** minus **6), reduction of power consumption and number of gates with low development costs.

Original languageEnglish
Pages (from-to)491-493
Number of pages3
JournalElectronics Letters
Volume22
Issue number9
Publication statusPublished - 1986 Jan 1

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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