The influence of Cu contamination from Cu through-silicon via (TSV) on device reliability in the 3-D LSI was electrically evaluated by capacitance-time (C-t) measurement. The Cu/Ta gate trench capacitors with two types of Ta barrier layers of 10-nm and 100-nm thicknesses (at the surface) were fabricated. The C-t curves of the trench capacitors with 10-nm thick Ta layer were severely degraded even after the initial annealing for 5 min at 300°C. It means that Cu atoms diffuse into the active area from the Cu TSV through scallop portions with extremely thin Ta layer in TSVs, and consequently, the generation lifetime of minority carrier is significantly reduced. However, the C-t curves of the trench capacitors with 100-nm thick Ta layer exhibit no change after annealing up to 60min. Based on the C-t evaluation results, we developed high reliable and fine-size of 5-μm diameter backside Cu TSV to achieve high reliability and high-end 3-D LSIs.