High-radix parallel VLSI dividers without using quotient digit selection tables

Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

This paper presents the design and evaluation of high-radix parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with less hardware complexity, in comparison with the binary counterparts. This paper also presents the experimental fabrication of the radix-4 divider in 0.35μm CMOS technology.

Original languageEnglish
Pages (from-to)345-352
Number of pages8
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2000 Jan 1
EventISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA
Duration: 2000 May 232000 May 25

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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