This paper presents the design and evaluation of high-radix parallel dividers for high-speed signal and data processing applications. The presented divider designs are based on the unified high-radix division algorithm proposed by the authors. By prescaling the operands and converting the representation of each partial remainder into partially non-redundant representation, the quotient digit can be obtained directly from the integer part of the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with less hardware complexity, in comparison with the binary counterparts. This paper also presents the experimental fabrication of the radix-4 divider in 0.35μm CMOS technology.
|Number of pages||8|
|Journal||Proceedings of The International Symposium on Multiple-Valued Logic|
|Publication status||Published - 2000 Jan 1|
|Event||ISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA|
Duration: 2000 May 23 → 2000 May 25
ASJC Scopus subject areas
- Computer Science(all)