High-performance VLSI processor for robot inverse dynamics computation

Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a VLSI-oriented matrix multiply-addition processor(MMP) for minimum-delay-time inverse dynamics computation on a linear array structure. We show that the delay time of the inverse dynamics computation becomes minimum based on the concept of the 'odd-even alternative computation'. The MMP architecture is systematically designed by using two types of data-dependence graphs of the 'odd-even alternative computation'. It is demonstrated by the layout evaluation that the MMP can be easily implemented in a single chip using the current VLSI technology. The performance with regard to the delay time is the highest in the architectures reported until now.

Original languageEnglish
Title of host publicationIEEE International Conference on Computer Design - VLSI in Computers and Processors
PublisherPubl by IEEE
Pages608-611
Number of pages4
ISBN (Print)0818622709
Publication statusPublished - 1991 Dec 1
EventProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91 - Cambridge, MA, USA
Duration: 1991 Oct 141991 Oct 16

Publication series

NameIEEE International Conference on Computer Design - VLSI in Computers and Processors

Other

OtherProceedings of the 1991 IEEE International Conference on Computer Design - VLSI in Computers and Processors - ICCD '91
CityCambridge, MA, USA
Period91/10/1491/10/16

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'High-performance VLSI processor for robot inverse dynamics computation'. Together they form a unique fingerprint.

Cite this