High-performance VLSI architecture for three-dimensional instrumentation based on a new concurrent memory-access scheme

Seunghwan Lee, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

A high-performance VLSI architecture for 3-D instrumentation is proposed based on a new concurrent memory access scheme. The key concept of this architecture is to reduce the number of pixel values to be retrieved and the time required in retrieving pixel values. Accordingly, the time required for the calculation of the MAD function is reduced and operations that involve memory access are calculated in parallel by a 2-D PE array in the MADU.

Original languageEnglish
Pages500-503
Number of pages4
Publication statusPublished - 1996 Dec 1
EventProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea
Duration: 1996 Nov 181996 Nov 21

Other

OtherProceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems
CitySeoul, South Korea
Period96/11/1896/11/21

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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