High-performance Si nanowire FET with a semi gate-around structure suitable for integration

Soshi Sato; Hideyuki Kamimura; Hideaki Arai; Kuniyuki Kakushima; Parhat Ahmet; Kenji Ohmori; Keisaku Yamada; Hiroshi Iwai

doi:10.1109/ESSDERC.2009.5331825

High-performance Si nanowire FET with a semi gate-around structure suitable for integration

Soshi Sato, Hideyuki Kamimura, Hideaki Arai, Kuniyuki Kakushima, Parhat Ahmet, Kenji Ohmori, Keisaku Yamada, Hiroshi Iwai

Center for Innovative Integrated Electronic Systems (CIES)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO₂ pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 μA at V _g/V_th=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate length (200 nm) and gate oxide thickness (5 nm) were relatively large, thanks to high mobility of 387 cm²/Vs. Regarding the off -current control, I_on/I _off ratio and S.S. were 10⁷ and 71 mV/dec., respectively. We discussed the case of multi-nanowire FET structure based our results. It can be concluded that multi-Si nanowire FET reveals much larger on-current than that of conventional planar FET.

Original language	English
Title of host publication	ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference
Pages	249-252
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2009.5331825
Publication status	Published - 2009
Event	39th European Solid-State Device Research Conference, ESSDERC 2009 - Athens, Greece Duration: 2009 Sept 14 → 2009 Sept 18

Publication series

Name	ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

Other

Other	39th European Solid-State Device Research Conference, ESSDERC 2009
Country/Territory	Greece
City	Athens
Period	09/9/14 → 09/9/18

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety Research

Access to Document

10.1109/ESSDERC.2009.5331825

Cite this

Sato, S., Kamimura, H., Arai, H., Kakushima, K., Ahmet, P., Ohmori, K., Yamada, K., & Iwai, H. (2009). High-performance Si nanowire FET with a semi gate-around structure suitable for integration. In ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference (pp. 249-252). [5331825] (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference). https://doi.org/10.1109/ESSDERC.2009.5331825

High-performance Si nanowire FET with a semi gate-around structure suitable for integration. / Sato, Soshi; Kamimura, Hideyuki; Arai, Hideaki et al.

ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference. 2009. p. 249-252 5331825 (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sato, S, Kamimura, H, Arai, H, Kakushima, K, Ahmet, P, Ohmori, K, Yamada, K & Iwai, H 2009, High-performance Si nanowire FET with a semi gate-around structure suitable for integration. in ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference., 5331825, ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference, pp. 249-252, 39th European Solid-State Device Research Conference, ESSDERC 2009, Athens, Greece, 09/9/14. https://doi.org/10.1109/ESSDERC.2009.5331825

Sato S, Kamimura H, Arai H, Kakushima K, Ahmet P, Ohmori K et al. High-performance Si nanowire FET with a semi gate-around structure suitable for integration. In ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference. 2009. p. 249-252. 5331825. (ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference). doi: 10.1109/ESSDERC.2009.5331825

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title = "High-performance Si nanowire FET with a semi gate-around structure suitable for integration",

abstract = "Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO2 pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 μA at V g/Vth=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate length (200 nm) and gate oxide thickness (5 nm) were relatively large, thanks to high mobility of 387 cm2/Vs. Regarding the off -current control, Ion/I off ratio and S.S. were 107 and 71 mV/dec., respectively. We discussed the case of multi-nanowire FET structure based our results. It can be concluded that multi-Si nanowire FET reveals much larger on-current than that of conventional planar FET.",

author = "Soshi Sato and Hideyuki Kamimura and Hideaki Arai and Kuniyuki Kakushima and Parhat Ahmet and Kenji Ohmori and Keisaku Yamada and Hiroshi Iwai",

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doi = "10.1109/ESSDERC.2009.5331825",

language = "English",

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pages = "249--252",

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T1 - High-performance Si nanowire FET with a semi gate-around structure suitable for integration

AU - Sato, Soshi

AU - Kamimura, Hideyuki

AU - Arai, Hideaki

AU - Kakushima, Kuniyuki

AU - Ahmet, Parhat

AU - Ohmori, Kenji

AU - Yamada, Keisaku

AU - Iwai, Hiroshi

PY - 2009

Y1 - 2009

N2 - Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO2 pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 μA at V g/Vth=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate length (200 nm) and gate oxide thickness (5 nm) were relatively large, thanks to high mobility of 387 cm2/Vs. Regarding the off -current control, Ion/I off ratio and S.S. were 107 and 71 mV/dec., respectively. We discussed the case of multi-nanowire FET structure based our results. It can be concluded that multi-Si nanowire FET reveals much larger on-current than that of conventional planar FET.

AB - Silicon Nanowire (Si NW) FETs with semi gate-around structures suitable for integration were fabricated using conventional planar CMOS processes. With the use of SiO2 pedestal and SiN sidewalls, lithography and etching steps over NW can be easily processed. A large on-current of 49.6 μA at V g/Vth=1.0 V has been obtained. This value is one of the highest current per nanowire, even though the gate length (200 nm) and gate oxide thickness (5 nm) were relatively large, thanks to high mobility of 387 cm2/Vs. Regarding the off -current control, Ion/I off ratio and S.S. were 107 and 71 mV/dec., respectively. We discussed the case of multi-nanowire FET structure based our results. It can be concluded that multi-Si nanowire FET reveals much larger on-current than that of conventional planar FET.

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BT - ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference

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Y2 - 14 September 2009 through 18 September 2009

ER -

High-performance Si nanowire FET with a semi gate-around structure suitable for integration

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