High-performance multiple-valued radix-2 signed-digit multiplier and its application

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to conferencePaperpeer-review

3 Citations (Scopus)

Abstract

The authors describe a high-speed compact radix-2 SD (signed digit) multiplier using multiple-valued current-mode logic circuits. A novel tree structure for the SD multiplier that uses four-input addition of partial products is proposed. The current-mode wired summation can be fully used for the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed.

Original languageEnglish
Pages125-126
Number of pages2
Publication statusPublished - 1989 Dec 1
EventSymposium on VLSI Circuits 1989 - Kyoto, Japan
Duration: 1989 May 251989 May 27

Other

OtherSymposium on VLSI Circuits 1989
CityKyoto, Japan
Period89/5/2589/5/27

ASJC Scopus subject areas

  • Engineering(all)

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