High-performance multiple-valued radix-2 signed-digit multiplier and its application

Shoji Kawahito; Michitaka Kameyama; Tatsuo Higuchi

High-performance multiple-valued radix-2 signed-digit multiplier and its application

Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi

INF - Computer and Mathematical Sciences

Research output: Contribution to conference › Paper › peer-review

3 Citations (Scopus)

Abstract

The authors describe a high-speed compact radix-2 SD (signed digit) multiplier using multiple-valued current-mode logic circuits. A novel tree structure for the SD multiplier that uses four-input addition of partial products is proposed. The current-mode wired summation can be fully used for the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed.

Original language	English
Pages	125-126
Number of pages	2
Publication status	Published - 1989 Dec 1
Event	Symposium on VLSI Circuits 1989 - Kyoto, Japan Duration: 1989 May 25 → 1989 May 27

Other

Other	Symposium on VLSI Circuits 1989
City	Kyoto, Japan
Period	89/5/25 → 89/5/27

ASJC Scopus subject areas

Engineering(all)

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abstract = "The authors describe a high-speed compact radix-2 SD (signed digit) multiplier using multiple-valued current-mode logic circuits. A novel tree structure for the SD multiplier that uses four-input addition of partial products is proposed. The current-mode wired summation can be fully used for the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed.",

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N2 - The authors describe a high-speed compact radix-2 SD (signed digit) multiplier using multiple-valued current-mode logic circuits. A novel tree structure for the SD multiplier that uses four-input addition of partial products is proposed. The current-mode wired summation can be fully used for the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed.

AB - The authors describe a high-speed compact radix-2 SD (signed digit) multiplier using multiple-valued current-mode logic circuits. A novel tree structure for the SD multiplier that uses four-input addition of partial products is proposed. The current-mode wired summation can be fully used for the structure, so that the number of full adders and interconnections can be drastically reduced. The implemented results of a prototype adder chip as the basic module are shown. Finally, an application to highly parallel vector inner product processing is discussed.

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