High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A new multiple-valued comparator based on active-load dual-rail differential logic is proposed for crosstalk-noise reduction while maintaining the switching speed. The use of dual-rail complementary differential-pair circuits (DPCs) whose outputs are summed up each other by wiring makes the common-mode noise reduced, yet the switching speed enhanced. By using the diode-connected cross-coupled PMOS active loads, the rapid transition behaviors in the DPC is relaxed appropriately, which can also eliminate a spike-shaped input noise. It is demonstrated in 0.18μm CMOS that the noise-reduction ratio and the switching delay of the proposed comparator is superior to those of a corresponding previous one.

Original languageEnglish
Title of host publication37th International Symposium on Multiple-Valued Logic, ISMVL 2007
DOIs
Publication statusPublished - 2007 Sep 3
Event37th International Symposium on Multiple-Valued Logic, ISMVL 2007 - Oslo, Norway
Duration: 2007 May 132007 May 16

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other37th International Symposium on Multiple-Valued Logic, ISMVL 2007
CountryNorway
CityOslo
Period07/5/1307/5/16

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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  • Cite this

    Mochizuki, A., Miura, M., & Hanyu, T. (2007). High-performance multiple-valued comparator based on active-load dual-rail differential logic for crosstalk-noise reduction. In 37th International Symposium on Multiple-Valued Logic, ISMVL 2007 [4215980] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2007.28