High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

H. Takato, K. Sunouchi, N. Okabe, Akihiro Nitayama, K. Hieda, F. Horiguchi, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

97 Citations (Scopus)

Abstract

A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge.

Original languageEnglish
Pages (from-to)222-225
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1988 Dec 1
EventTechnical Digest - International Electron Devices Meeting 1988 - San Francisco, CA, USA
Duration: 1988 Dec 111988 Dec 14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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