High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Makoto Iwai, Yasue Yamamoto, Ryohsuke Nishi, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)


We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

Original languageEnglish
Pages (from-to)6904-6906
Number of pages3
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number10
Publication statusPublished - 2004 Oct


  • Burled gate
  • Surrounding gate transistor
  • Three-dimensional device

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


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