Abstract
We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.
| Original language | English |
|---|---|
| Pages (from-to) | 6904-6906 |
| Number of pages | 3 |
| Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
| Volume | 43 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2004 Oct 1 |
Keywords
- Burled gate
- Surrounding gate transistor
- Three-dimensional device
ASJC Scopus subject areas
- Engineering(all)
- Physics and Astronomy(all)
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Cite this
Iwai, M., Yamamoto, Y., Nishi, R., Sakuraba, H., Endoh, T., & Masuoka, F. (2004). High-performance buried-gate surrounding gate transistor for future three-dimensional devices. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 43(10), 6904-6906. https://doi.org/10.1143/JJAP.43.6904