High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Makoto Iwai; Yasue Yamamoto; Ryohsuke Nishi; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka

doi:10.1143/JJAP.43.6904

High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Makoto Iwai, Yasue Yamamoto, Ryohsuke Nishi, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

ENG - Electrical Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

Original language	English
Pages (from-to)	6904-6906
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	43
Issue number	10
DOIs	https://doi.org/10.1143/JJAP.43.6904
Publication status	Published - 2004 Oct

Keywords

Burled gate
Surrounding gate transistor
Three-dimensional device

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

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10.1143/JJAP.43.6904

Cite this

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abstract = "We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.",

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AU - Yamamoto, Yasue

AU - Nishi, Ryohsuke

AU - Sakuraba, Hiroshi

AU - Endoh, Tetsuo

AU - Masuoka, Fujio

PY - 2004/10

Y1 - 2004/10

N2 - We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

AB - We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

KW - Burled gate

KW - Surrounding gate transistor

KW - Three-dimensional device

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JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 10

ER -

High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Abstract

Keywords

ASJC Scopus subject areas

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