High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Makoto Iwai; Yasue Yamamoto; Ryohsuke Nishi; Hiroshi Sakuraba; Tetsuo Endoh; Fujio Masuoka

doi:10.1143/JJAP.43.6904

High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Makoto Iwai, Yasue Yamamoto, Ryohsuke Nishi, Hiroshi Sakuraba, Tetsuo Endoh, Fujio Masuoka

ENG - Electrical Engineering

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

Original language	English
Pages (from-to)	6904-6906
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	43
Issue number	10
DOIs	https://doi.org/10.1143/JJAP.43.6904
Publication status	Published - 2004 Oct 1

Keywords

Burled gate
Surrounding gate transistor
Three-dimensional device

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

Access to Document

10.1143/JJAP.43.6904

Cite this

High-performance buried-gate surrounding gate transistor for future three-dimensional devices. / Iwai, Makoto; Yamamoto, Yasue; Nishi, Ryohsuke; Sakuraba, Hiroshi; Endoh, Tetsuo; Masuoka, Fujio.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 43, No. 10, 01.10.2004, p. 6904-6906.

Research output: Contribution to journal › Article › peer-review

@article{67a6b5604a6742b2be5543ce0cbaa4a0,

title = "High-performance buried-gate surrounding gate transistor for future three-dimensional devices",

abstract = "We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.",

keywords = "Burled gate, Surrounding gate transistor, Three-dimensional device",

author = "Makoto Iwai and Yasue Yamamoto and Ryohsuke Nishi and Hiroshi Sakuraba and Tetsuo Endoh and Fujio Masuoka",

year = "2004",

month = oct,

day = "1",

doi = "10.1143/JJAP.43.6904",

language = "English",

volume = "43",

pages = "6904--6906",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "10",

}

TY - JOUR

T1 - High-performance buried-gate surrounding gate transistor for future three-dimensional devices

AU - Iwai, Makoto

AU - Yamamoto, Yasue

AU - Nishi, Ryohsuke

AU - Sakuraba, Hiroshi

AU - Endoh, Tetsuo

AU - Masuoka, Fujio

PY - 2004/10/1

Y1 - 2004/10/1

N2 - We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

AB - We propose the buried-gate surrounding gate transistor (BG-SGT) as a high-performance transistor. The occupied area of BG-SGT can be shrunk to 50% of that of the planar transistor. Moreover, decreasing the body pillar size leads to a steep subthreshold slope. Because of these features, BG-SGT is extremely attractive for future three-dimensional devices.

KW - Burled gate

KW - Surrounding gate transistor

KW - Three-dimensional device

UR - http://www.scopus.com/inward/record.url?scp=10844281711&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=10844281711&partnerID=8YFLogxK

U2 - 10.1143/JJAP.43.6904

DO - 10.1143/JJAP.43.6904

M3 - Article

AN - SCOPUS:10844281711

VL - 43

SP - 6904

EP - 6906

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 10

ER -

High-performance buried-gate surrounding gate transistor for future three-dimensional devices

Abstract

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this