High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique

T. Ando; T. Hirano; K. Tai; S. Yamaguchi; K. Tanaka; I. Oshiyama; M. Nakata; K. Watanabe; R. Yamamoto; S. Kanda; Y. Tateshita; H. Wakabayashi; Y. Tagawa; M. Tsukamoto; H. Iwamoto; M. Saito; S. Toyoda; H. Kumigashira; M. Oshima; N. Nagashima; S. Kadomura

doi:10.1109/VTSA.2007.378913

High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique

T. Ando, T. Hirano, K. Tai, S. Yamaguchi, K. Tanaka, I. Oshiyama, M. Nakata, K. Watanabe, R. Yamamoto, S. Kanda, Y. Tateshita, H. Wakabayashi, Y. Tagawa, M. Tsukamoto, H. Iwamoto, M. Saito, S. Toyoda, H. Kumigashira, M. Oshima, N. NagashimaS. Kadomura

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The impacts of interfacial layer (IFL) thickness and crystallinity of HfO₂/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSi_x/HfO₂) and pFETs (Ru/HfO ₂) including BTI. It was found that crystallization of HfO ₂ causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO ₂ thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO₂/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500°C for the very first time.

Original language	English
Title of host publication	2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	1424405858, 9781424405855
DOIs	https://doi.org/10.1109/VTSA.2007.378913
Publication status	Published - 2007
Externally published	Yes
Event	2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China Duration: 2007 Apr 23 → 2007 Apr 25

Publication series

Name	International Symposium on VLSI Technology, Systems, and Applications, Proceedings
ISSN (Print)	1930-8868

Other

Other	2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Country	Taiwan, Province of China
City	Hsinchu
Period	07/4/23 → 07/4/25

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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Ando, T., Hirano, T., Tai, K., Yamaguchi, S., Tanaka, K., Oshiyama, I., Nakata, M., Watanabe, K., Yamamoto, R., Kanda, S., Tateshita, Y., Wakabayashi, H., Tagawa, Y., Tsukamoto, M., Iwamoto, H., Saito, M., Toyoda, S., Kumigashira, H., Oshima, M., ... Kadomura, S. (2007). High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique. In 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers [4239481] (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VTSA.2007.378913

High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique. / Ando, T.; Hirano, T.; Tai, K.; Yamaguchi, S.; Tanaka, K.; Oshiyama, I.; Nakata, M.; Watanabe, K.; Yamamoto, R.; Kanda, S.; Tateshita, Y.; Wakabayashi, H.; Tagawa, Y.; Tsukamoto, M.; Iwamoto, H.; Saito, M.; Toyoda, S.; Kumigashira, H.; Oshima, M.; Nagashima, N.; Kadomura, S.

2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. 4239481 (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ando, T, Hirano, T, Tai, K, Yamaguchi, S, Tanaka, K, Oshiyama, I, Nakata, M, Watanabe, K, Yamamoto, R, Kanda, S, Tateshita, Y, Wakabayashi, H, Tagawa, Y, Tsukamoto, M, Iwamoto, H, Saito, M, Toyoda, S , Kumigashira, H, Oshima, M, Nagashima, N & Kadomura, S 2007, High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique. in 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers., 4239481, International Symposium on VLSI Technology, Systems, and Applications, Proceedings, Institute of Electrical and Electronics Engineers Inc., 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 07/4/23. https://doi.org/10.1109/VTSA.2007.378913

Ando T, Hirano T, Tai K, Yamaguchi S, Tanaka K, Oshiyama I et al. High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique. In 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. 4239481. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings). https://doi.org/10.1109/VTSA.2007.378913

Ando, T. ; Hirano, T. ; Tai, K. ; Yamaguchi, S. ; Tanaka, K. ; Oshiyama, I. ; Nakata, M. ; Watanabe, K. ; Yamamoto, R. ; Kanda, S. ; Tateshita, Y. ; Wakabayashi, H. ; Tagawa, Y. ; Tsukamoto, M. ; Iwamoto, H. ; Saito, M. ; Toyoda, S. ; Kumigashira, H. ; Oshima, M. ; Nagashima, N. ; Kadomura, S. / High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique. 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. (International Symposium on VLSI Technology, Systems, and Applications, Proceedings).

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title = "High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique",

abstract = "The impacts of interfacial layer (IFL) thickness and crystallinity of HfO2/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSix/HfO2) and pFETs (Ru/HfO 2) including BTI. It was found that crystallization of HfO 2 causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO 2 thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO2/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500°C for the very first time.",

author = "T. Ando and T. Hirano and K. Tai and S. Yamaguchi and K. Tanaka and I. Oshiyama and M. Nakata and K. Watanabe and R. Yamamoto and S. Kanda and Y. Tateshita and H. Wakabayashi and Y. Tagawa and M. Tsukamoto and H. Iwamoto and M. Saito and S. Toyoda and H. Kumigashira and M. Oshima and N. Nagashima and S. Kadomura",

note = "Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA ; Conference date: 23-04-2007 Through 25-04-2007",

year = "2007",

doi = "10.1109/VTSA.2007.378913",

language = "English",

isbn = "1424405858",

series = "International Symposium on VLSI Technology, Systems, and Applications, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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T1 - High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique

AU - Ando, T.

AU - Hirano, T.

AU - Tai, K.

AU - Yamaguchi, S.

AU - Tanaka, K.

AU - Oshiyama, I.

AU - Nakata, M.

AU - Watanabe, K.

AU - Yamamoto, R.

AU - Kanda, S.

AU - Tateshita, Y.

AU - Wakabayashi, H.

AU - Tagawa, Y.

AU - Tsukamoto, M.

AU - Iwamoto, H.

AU - Saito, M.

AU - Toyoda, S.

AU - Kumigashira, H.

AU - Oshima, M.

AU - Nagashima, N.

AU - Kadomura, S.

PY - 2007

Y1 - 2007

N2 - The impacts of interfacial layer (IFL) thickness and crystallinity of HfO2/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSix/HfO2) and pFETs (Ru/HfO 2) including BTI. It was found that crystallization of HfO 2 causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO 2 thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO2/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500°C for the very first time.

AB - The impacts of interfacial layer (IFL) thickness and crystallinity of HfO2/IFL bi-layer on electrical properties were clarified using synchrotron radiation photoemission spectroscopy (SRPES) and electrical measurements of nFETs (HfSix/HfO2) and pFETs (Ru/HfO 2) including BTI. It was found that crystallization of HfO 2 causes significant degradation in electron mobility and PBTI, whereas the impacts on hole mobility and NBTI are negligible. The SRPES measurement revealed that the crystallization temperature depends on HfO 2 thickness. We also found that the IFL thickness is the dominant factor for both electron mobility and PBTI. Therefore, a careful optimization of the HfO2/IFL bi-layer is indispensable. We proposed a novel technique for controlling the bi-layer thickness and demonstrated dual metal CMOS devices with high mobility and high reliability even by a post high-k process lower than 500°C for the very first time.

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M3 - Conference contribution

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BT - 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

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Y2 - 23 April 2007 through 25 April 2007

ER -

High performance and high reliability dual metal CMOS gate stacks using novel high-k Bi-layer control technique

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