High performance 0.2 μm dual gate complementary MOS technologies by suppression of transient-enhanced-diffusion using rapid thermal annealing

Yukio Nishida, Hirokazu Sayama, Satoshi Shimizu, Takashi Kuroi, Akihiko Furukawa, Akinobu Teramoto, Tetsuya Uchida, Yasuo Inoue, Tadashi Nishimura

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Rapid thermal annealing (RTA) before the low temperature process is introduced in the 0.2 μm dual gate complementary metal oxide semiconductor (CMOS) process and its effect has been systematically investigated. Channel profiles of boron and phosphorus remain steep by the additional RTA process before gate oxidation, as seen by using secondary ion mass spectrometry and a simulation with the point defect based diffusion model. The most effective temperature to suppress transient-enhanced-diffusion (TED) is 900-1000°C, which can be remarkably suppressed by a 30s treatment in the case of 900°C RTA. A steep channel profile decreases the threshold voltage and increases the transconductance. Shallow source/drain extension profiles of BF2 and phosphorus can be fabricated by an additional RTA process before sidewall spacer film deposition, which can improve the threshold voltage lowering. Consequently, a high current drivability of a 0.2 μm CMOS has been achieved by the suppression of TED using two additional RTA processes.

Original languageEnglish
Pages (from-to)1054-1058
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume37
Issue number3 SUPPL. B
DOIs
Publication statusPublished - 1998 Mar

Keywords

  • Channel engineering
  • Dual gate CMOS
  • MOSFET
  • Point defect
  • Rapid thermal annealing
  • Silicon
  • Transient-enhanced-diffusion

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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