TY - GEN
T1 - High-level design of multiple-valued arithmetic circuits based on arithmetic description language
AU - Watanabe, Yuki
AU - Homma, Naofumi
AU - Degawa, Katsuhiko
AU - Aoki, Takafumi
AU - Higuchi, Tatsuo
PY - 2008/9/3
Y1 - 2008/9/3
N2 - This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35μm CMOS technology, and demonstrate that the proposed method can synthesize a 32x32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.
AB - This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35μm CMOS technology, and demonstrate that the proposed method can synthesize a 32x32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.
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U2 - 10.1109/ISMVL.2008.39
DO - 10.1109/ISMVL.2008.39
M3 - Conference contribution
AN - SCOPUS:50449108327
SN - 9780769531557
T3 - Proceedings of The International Symposium on Multiple-Valued Logic
SP - 112
EP - 117
BT - Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
T2 - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Y2 - 22 May 2008 through 24 May 2008
ER -