High-level design of multiple-valued arithmetic circuits based on arithmetic description language

Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelf place-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35μm CMOS technology, and demonstrate that the proposed method can synthesize a 32x32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.

Original languageEnglish
Title of host publicationProceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008
Pages112-117
Number of pages6
DOIs
Publication statusPublished - 2008 Sep 3
Event38th International Symposium on Multiple-Valued Logic, ISMVL 2008 - Dallas, TX, United States
Duration: 2008 May 222008 May 24

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other38th International Symposium on Multiple-Valued Logic, ISMVL 2008
CountryUnited States
CityDallas, TX
Period08/5/2208/5/24

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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    Watanabe, Y., Homma, N., Degawa, K., Aoki, T., & Higuchi, T. (2008). High-level design of multiple-valued arithmetic circuits based on arithmetic description language. In Proceedings - 38th International Symposium on Multiple-Valued Logic, ISMVL 2008 (pp. 112-117). [4539411] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2008.39