TY - JOUR
T1 - High-density through silicon vias for 3-D LSIs
AU - Koyanagi, Mitsumasa
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
N1 - Funding Information:
Prof. Koyanagi received the 2006 IEEE Jun-ichi Nishizawa Medal, the 1996 IEEE Cledo Brunetti Award, the 2001 Award of Ministry of Education, Culture, Sports, Science and Technology, the 1994 Solid-State Devices and Materials Award, the 2004 Optoelectronic Technology Achievement Award from the Japan Society of Applied Physics, and the 1990 Okouchi Prize.
PY - 2009
Y1 - 2009
N2 - High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.
AB - High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.
KW - 3-D system-in-package (SiP)
KW - Microbump
KW - Three-dimensional (3-D) large-scale integration (LSI)
KW - Through silicon via (TSV)
KW - Wafer bonding
KW - Wafer thinning
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U2 - 10.1109/JPROC.2008.2007463
DO - 10.1109/JPROC.2008.2007463
M3 - Article
AN - SCOPUS:61549132828
SN - 0018-9219
VL - 97
SP - 49
EP - 60
JO - Proceedings of the Institute of Radio Engineers
JF - Proceedings of the Institute of Radio Engineers
IS - 1
M1 - 4796288
ER -