High-density quaternary logic array chip for knowledge information processing systems

Takahiro Hanyu, Tatsuo Higuchi

Research output: Contribution to conferencePaperpeer-review

1 Citation (Scopus)

Abstract

A high-density quaternary logic array chip for high-speed pattern matching is discussed. Double pattern matching is performed by one transistor cell in the quaternary logic array. As a result, the chip area can be reduced by 30% compared to the corresponding binary logic array. A highly parallel pattern-matching scheme makes high-speed reasoning possible. Moreover, the quaternary logic array can be easily implemented by a standard NMOS process with multiple ion implants.

Original languageEnglish
Pages29-30
Number of pages2
Publication statusPublished - 1988 Dec 1
Event1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan
Duration: 1988 Aug 221988 Aug 24

Other

Other1988 Symposium on VLSI Circuits - Digest of Technical Papers
CityTokyo, Japan
Period88/8/2288/8/24

ASJC Scopus subject areas

  • Engineering(all)

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