A high-density quaternary logic array chip for high-speed pattern matching is discussed. Double pattern matching is performed by one transistor cell in the quaternary logic array. As a result, the chip area can be reduced by 30% compared to the corresponding binary logic array. A highly parallel pattern-matching scheme makes high-speed reasoning possible. Moreover, the quaternary logic array can be easily implemented by a standard NMOS process with multiple ion implants.
|Number of pages||2|
|Publication status||Published - 1988 Dec 1|
|Event||1988 Symposium on VLSI Circuits - Digest of Technical Papers - Tokyo, Japan|
Duration: 1988 Aug 22 → 1988 Aug 24
|Other||1988 Symposium on VLSI Circuits - Digest of Technical Papers|
|Period||88/8/22 → 88/8/24|
ASJC Scopus subject areas