A new high-density NMOS logic array chip based on quaternary logic is implemented for high-speed parallel pattern matching in a knowledge information processing system. The logic array can be exploited in real-time applications when the rules are fixed. Based on the appropriate quaternary coding for the contents of working memory and production memory, a double-pattern-matching algorithm is proposed for achieving a high-density chip. One of four states for 2-bit information concerning two elements of a rule is stored into a pattern-matching cell by multiple ion implants, so that the pattern-matching cell is implemented using only a single transistor. It is demonstrated that the chip area for pattern matching is reduced by 30 percent compared with the corresponding binary logic array.
ASJC Scopus subject areas
- Electrical and Electronic Engineering