High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

Yoshiro Shimojo, Atsushi Konno, Jun Nishimura, Takayuki Okada, Yuki Yamada, Soichiro Kitazaki, Hironobu Furuhashi, Soichi Yamazaki, Katsunori Yahashi, Kazuhiro Tomioka, Yoshihiro Minami, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Tohru Ozaki, Hidehiro Shiga, Tadashi Miyakawa, Shinichiro Shiratake, Daisaburo Takashima, Iwao KunishimaTakeshi Hamamoto, Akihiro Nitayama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Citations (Scopus)

Abstract

Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128Mb chain FeRAMTM with SDRAM-compatible 1.6GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60fF is also installed [1]. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128Mb 1T1C operation.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages218-219
Number of pages2
Publication statusPublished - 2009 Nov 16
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period09/6/1609/6/18

Keywords

  • 128Mb
  • Chain and hydrogen barrier
  • FeRAM

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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