Abstract
To overcome various concerns caused by scaling-down the device size, it is indispensable to introduce a new concept of heterogeneous 3D integration called a super-chip in which various kinds of device chips with different size, different devices and different materials are stacked. A key technology of self-assembly and electrostatic (SAE) temporary bonding has been developed to achieve a super-chip. Several kinds of super-chips are fabricated by stacking compound semiconductor device chip, photonic device chip and spintronic device chip on CMOS device chips.
| Original language | English |
|---|---|
| Title of host publication | 2013 IEEE International Electron Devices Meeting, IEDM 2013 |
| DOIs | |
| Publication status | Published - 2013 Dec 1 |
| Event | 2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States Duration: 2013 Dec 9 → 2013 Dec 11 |
Publication series
| Name | Technical Digest - International Electron Devices Meeting, IEDM |
|---|---|
| ISSN (Print) | 0163-1918 |
Other
| Other | 2013 IEEE International Electron Devices Meeting, IEDM 2013 |
|---|---|
| Country | United States |
| City | Washington, DC |
| Period | 13/12/9 → 13/12/11 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
- Materials Chemistry
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Cite this
Koyanagi, M. (2013). Heterogeneous 3D integration - Technology enabler toward future super-chip. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 [6724539] (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724539