Heterogeneous 3D integration technology and new 3D LSIs

Mitsumasa Koyanagi, Kanuku Ri, Takafumi Fukushima, Tetsu Tanaka

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A new 3-D integration technology and heterogeneous integration technology called a super-chip integration is described. A number of known good dies (KGDs) with different sizes and different devices are simultaneously aligned and bonded onto lower chips or wafer by a chip self-assembly method using the surface tension of liquid in the super-chip integration. Possibilities for new system-on-a chip and heterogeneous LSIs by 3D super-chip integration such as 3D stacked multicore processor with self-test and self-repair function, GPU stacked 3D image sensor with extremely fast processing speed and 3D stacked reconfigurable processor with spin memory are discussed.

Original languageEnglish
Title of host publicationICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
DOIs
Publication statusPublished - 2012 Dec 1
Event2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012 - Xi'an, China
Duration: 2012 Oct 292012 Nov 1

Publication series

NameICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2012
CountryChina
CityXi'an
Period12/10/2912/11/1

ASJC Scopus subject areas

  • Human-Computer Interaction
  • Electrical and Electronic Engineering

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