Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge

Josep Angel Oltra-Oltra; Bernardo Vallejo; Jordi Madrenas; Diana Mata-Hernandez; Mireya Zapata; Shigeo Sato

doi:10.1109/ISCAS51556.2021.9401615

Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge

Josep Angel Oltra-Oltra, Bernardo Vallejo, Jordi Madrenas, Diana Mata-Hernandez, Mireya Zapata, Shigeo Sato

Information Devices Division

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.

Original language	English
Title of host publication	2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728192017
DOIs	https://doi.org/10.1109/ISCAS51556.2021.9401615
Publication status	Published - 2021
Event	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of Duration: 2021 May 22 → 2021 May 28

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2021-May
ISSN (Print)	0271-4310

Conference

Conference	53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/Territory	Korea, Republic of
City	Daegu
Period	21/5/22 → 21/5/28

Keywords

Edge Computing
HEENS
Hardware-Software Integration
Neural Computing
SNAVA
SNN
Spiking Neural Networks

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ISCAS51556.2021.9401615

Cite this

Oltra-Oltra, J. A., Vallejo, B., Madrenas, J., Mata-Hernandez, D., Zapata, M., & Sato, S. (2021). Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings [9401615] (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS51556.2021.9401615

Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge. / Oltra-Oltra, Josep Angel; Vallejo, Bernardo; Madrenas, Jordi; Mata-Hernandez, Diana; Zapata, Mireya; Sato, Shigeo.

2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9401615 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2021-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Oltra-Oltra, JA, Vallejo, B, Madrenas, J, Mata-Hernandez, D, Zapata, M & Sato, S 2021, Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge. in 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings., 9401615, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2021-May, Institute of Electrical and Electronics Engineers Inc., 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, Korea, Republic of, 21/5/22. https://doi.org/10.1109/ISCAS51556.2021.9401615

Oltra-Oltra JA, Vallejo B, Madrenas J, Mata-Hernandez D, Zapata M, Sato S. Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge. In 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9401615. (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS51556.2021.9401615

Oltra-Oltra, Josep Angel ; Vallejo, Bernardo ; Madrenas, Jordi ; Mata-Hernandez, Diana ; Zapata, Mireya ; Sato, Shigeo. / Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge. 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{35c49080ff5a4f8bbe7810b8222ce6c4,

title = "Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge",

abstract = "This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.",

keywords = "Edge Computing, HEENS, Hardware-Software Integration, Neural Computing, SNAVA, SNN, Spiking Neural Networks",

author = "Oltra-Oltra, {Josep Angel} and Bernardo Vallejo and Jordi Madrenas and Diana Mata-Hernandez and Mireya Zapata and Shigeo Sato",

note = "Funding Information: Work supported in part under project RTI2018-099766-B-I00 by the Spanish Ministry of Science, Innovation and Universities, the State Research Agency (AEI), and the European Social Fund (ESF). Publisher Copyright: {\textcopyright} 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.; 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 ; Conference date: 22-05-2021 Through 28-05-2021",

year = "2021",

doi = "10.1109/ISCAS51556.2021.9401615",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings",

}

TY - GEN

T1 - Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge

AU - Oltra-Oltra, Josep Angel

AU - Vallejo, Bernardo

AU - Madrenas, Jordi

AU - Mata-Hernandez, Diana

AU - Zapata, Mireya

AU - Sato, Shigeo

N1 - Funding Information: Work supported in part under project RTI2018-099766-B-I00 by the Spanish Ministry of Science, Innovation and Universities, the State Research Agency (AEI), and the European Social Fund (ESF). Publisher Copyright: © 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.

PY - 2021

Y1 - 2021

N2 - This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.

AB - This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.

KW - Edge Computing

KW - HEENS

KW - Hardware-Software Integration

KW - Neural Computing

KW - SNAVA

KW - SNN

KW - Spiking Neural Networks

UR - http://www.scopus.com/inward/record.url?scp=85109010457&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85109010457&partnerID=8YFLogxK

U2 - 10.1109/ISCAS51556.2021.9401615

DO - 10.1109/ISCAS51556.2021.9401615

M3 - Conference contribution

AN - SCOPUS:85109010457

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021

Y2 - 22 May 2021 through 28 May 2021

ER -

Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge

Abstract

Publication series

Conference

Keywords

ASJC Scopus subject areas

Access to Document

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