TY - GEN
T1 - Hardware-software co-design for efficient and scalable real-time emulation of SNNs on the edge
AU - Oltra-Oltra, Josep Angel
AU - Vallejo, Bernardo
AU - Madrenas, Jordi
AU - Mata-Hernandez, Diana
AU - Zapata, Mireya
AU - Sato, Shigeo
N1 - Funding Information:
Work supported in part under project RTI2018-099766-B-I00 by the Spanish Ministry of Science, Innovation and Universities, the State Research Agency (AEI), and the European Social Fund (ESF).
Publisher Copyright:
© 2021 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 2021
Y1 - 2021
N2 - This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.
AB - This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.
KW - Edge Computing
KW - HEENS
KW - Hardware-Software Integration
KW - Neural Computing
KW - SNAVA
KW - SNN
KW - Spiking Neural Networks
UR - http://www.scopus.com/inward/record.url?scp=85109010457&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85109010457&partnerID=8YFLogxK
U2 - 10.1109/ISCAS51556.2021.9401615
DO - 10.1109/ISCAS51556.2021.9401615
M3 - Conference contribution
AN - SCOPUS:85109010457
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
BT - 2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Y2 - 22 May 2021 through 28 May 2021
ER -