Hardware-learning neural network LSI using a highly-functional transistor simulating neuron actions

Hiroshi Ishii, Tadashi Shibata, Hideo Kosaka, Tadahiro Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes the architecture and the organization of a hardware-learning neural network LSI, in which a newly developed 'brain-cell-like' transistor called Neuron MOSFET (neuMOS or vMOS) is utilized not only in a neuron cell but also in a synapse cell. In order to implement learning capability on a chip, a new hardware-oriented backpropagation learning algorithm has been developed. The actions for self-learning based on this algorithm are also carried out by vMOS logic circuits.

Original languageEnglish
Title of host publicationProceedings of the International Joint Conference on Neural Networks
PublisherPubl by IEEE
Pages907-910
Number of pages4
ISBN (Print)0780314212, 9780780314214
Publication statusPublished - 1993 Dec 1
EventProceedings of 1993 International Joint Conference on Neural Networks. Part 1 (of 3) - Nagoya, Jpn
Duration: 1993 Oct 251993 Oct 29

Publication series

NameProceedings of the International Joint Conference on Neural Networks
Volume1

Other

OtherProceedings of 1993 International Joint Conference on Neural Networks. Part 1 (of 3)
CityNagoya, Jpn
Period93/10/2593/10/29

ASJC Scopus subject areas

  • Software
  • Artificial Intelligence

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