Hardware implementations of hash function Luffa

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents hardware architectures for the hash algorithm Luffa, which is a candidate for the next-generation hash standard SHA-3. The architectures were implemented by using a 90-nm CMOS standard cell library. A high throughput of 35 Gbps for a high-speed architecture and a gate count of 14.7 kgate for a compact architecture were obtained. In comparison with Keccak, other SHA-3 candidate in the sponge function category, as well as with the current hash standard SHA-256, Luffa exhibited the advantage of flexible implementation ranging from high-speed to compact circuits.

Original languageEnglish
Title of host publicationProceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
Pages130-134
Number of pages5
DOIs
Publication statusPublished - 2010 Aug 24
Event2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010 - Anaheim, CA, United States
Duration: 2010 Jun 132010 Jun 14

Publication series

NameProceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010

Other

Other2010 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2010
CountryUnited States
CityAnaheim, CA
Period10/6/1310/6/14

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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