This paper designs and implements a hardware-based evolutionary digital filter (EDF). The EDF is an adaptive digital filter which is controlled by adaptive algorithm based on evolutionary computation. The hardware-based EDF consists of two submodules, that is, a filtering and fitness calculation (FFC) module and a reproduction and selection (RS) module. The FFC module has high computational ability to calculate the output and the fitness value since its submodules run in parallel. A synthesis result of the designed chip shows the clock frequency is 20.0MHz and the maximum sampling rate of the EDF is 3.7kHz. Moreover, the hardware-based EDF with 21 submodules of the FFC is 2.2 times faster than the software-based EDF.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2003 Jul 14|
|Event||Proceedings of the 2003 IEEE International Symposium on Circuits and Systems - Bangkok, Thailand|
Duration: 2003 May 25 → 2003 May 28
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering