Hardware implementation of an inverse function delayed neural network using stochastic logic

Hongge Li, Yoshihiro Hayakawa, Shigeo Sato, Koji Nakajima

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


In this paper, the authors present a new digital circuit of neuron hardware using a field programmable gate array (FPGA). A new Inverse function Delayed (ID) neuron model is implemented. The Inverse function Delayed model, which includes the BVP model, has superior associative properties thanks to negative resistance. An associative memory based on the ID model with self-connections has possibilities of improving its basin sizes and memory capacity. In order to decrease circuit area, we employ stochastic logic. The proposed neuron circuit completes the stimulus response output, and its retrieval property with negative resistance is superior to a conventional nonlinear model in basin size of an associative memory.

Original languageEnglish
Pages (from-to)2572-2578
Number of pages7
JournalIEICE Transactions on Information and Systems
Issue number9
Publication statusPublished - 2006
Externally publishedYes


  • Associative memory
  • Field programmable gate array (FPGA)
  • Inverse function delayed model
  • Stochastic logic

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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