TY - JOUR
T1 - Generation of STDP with non-volatile tunnel-FET memory for large-scale and low-power spiking neural networks
AU - Kino, Hisashi
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
N1 - Funding Information:
This study was supported by the Frontier Research Institute for Interdisciplinary Sciences (FRIS) Tohoku University. It was also supported by the VLSI Design and Education Center (VDEC), the University of Tokyo, in collaboration with Cadence Design Systems. This study was conducted in the Micro/Nano-Machining Research and Education Center at Tohoku University.
Funding Information:
This work was supported by Japan Society for the Promotion of Science KAKENHI under Grant JP19K21953.
Publisher Copyright:
© 2013 IEEE.
PY - 2020
Y1 - 2020
N2 - Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This article reports the I-V, programming, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.
AB - Spiking neural networks (SNNs) have attracted considerable attention as next-generation neural networks. As SNNs consist of devices that have spike-timing-dependent plasticity (STDP) characteristics, STDP is one of the critical characteristics we need to consider to implement an SNN. In this study, we generated the STDP of a biological synapse with non-volatile tunnel-field-effect-transistor (tunnel FET) memory that has a charge-storage layer and a tunnel FET structure. Tunnel FET is a promising structure to reduce the operation voltage owing to its steep sub-threshold slope. Therefore, the non-volatile tunnel-FET memory we propose enables the implementation of low-operation-voltage SNNs. This article reports the I-V, programming, and both symmetric and asymmetric STDP characteristics of a non-volatile tunnel-FET memory with p-channel-MOS-like operation.
KW - MONOS
KW - Spiking neural network
KW - spike-timing-dependent plasticity
KW - synaptic device
KW - tunnel FET
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U2 - 10.1109/JEDS.2020.3025336
DO - 10.1109/JEDS.2020.3025336
M3 - Article
AN - SCOPUS:85095967327
SN - 2168-6734
VL - 8
SP - 1266
EP - 1271
JO - IEEE Journal of the Electron Devices Society
JF - IEEE Journal of the Electron Devices Society
M1 - 9201106
ER -