Gate length scaling of high-k vertical MOSFET toward 20nm CMOS technology and beyond

Takeshi Sasaki, Tetsuo Endoh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents the gate length scaling of the Vertical MOSFET (VMOS) with high-k dielectrics for beyond 20nm CMOS technology in comparison with Double Gate MOSFET (DG) at the same Drain Induced Barrier Lowering (DIBL). The VMOS can significantly suppresses DIBL within 11mV/V caused by fringing electric field through thicker designed high-k dielectrics (EOT=1.0nm). Moreover, the VMOS can be designed by shorter gate length from 5.4 to 19nm as using higher gate dielectric constant from k=10 to k=60.

Original languageEnglish
Title of host publication2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
PublisherIEEE Computer Society
ISBN (Print)9781479913602
DOIs
Publication statusPublished - 2013 Jan 1
Event2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013 - Monterey, CA, United States
Duration: 2013 Oct 72013 Oct 10

Publication series

Name2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013

Other

Other2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2013
Country/TerritoryUnited States
CityMonterey, CA
Period13/10/713/10/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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