This paper describes a gate-array layout system, LOP-ARP2, as a subsystem of Packaging Automation System (PAS), which is a total design system for digital circuits. A new placement technique is proposed: Hierarchical Force Directed Technique considering Circuit Structure, which has been proved to be efficient to large scale gate-arrays.
|Number of pages||12|
|Journal||Journal of the Faculty of Engineering, University of Tokyo, Series B|
|Publication status||Published - 1984 Sep 1|
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