Abstract
This paper presents a GA-based design method for multiplierless 2-D state-space digital filters (SSDFs) with very small roundoff noise. All coefficients of the designed 2-D SSDFs are expressed as the sum of two powers-of-two terms. Consequently, the multiplierless 2-D SSDFs are attractive for the high-speed operation and simplification of hardware, since the signal in the filters can be processed by fewer shifting operations and additions instead of multiplications. The proposed method can design multiplierless 2-D SSDFs without significantly increasing the roundoff noise power gain and with smaller approximation error than those of the other methods which use transfer functions in a continuous coefficient space. The effectiveness of the proposed method is demonstrated with a design example.
Original language | English |
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Pages (from-to) | 1283-1286 |
Number of pages | 4 |
Journal | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
Volume | 3 |
Publication status | Published - 1996 Jan 1 |
Event | Proceedings of the 1996 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP. Part 1 (of 6) - Atlanta, GA, USA Duration: 1996 May 7 → 1996 May 10 |
ASJC Scopus subject areas
- Software
- Signal Processing
- Electrical and Electronic Engineering